1. Field of the Invention
This invention relates to a trace control circuit constituting a part of a debugging circuit built into a microcomputer.
2. Description of the Related Art
Generally speaking, an in-circuit emulator (ICE) is used for program debugging in a microcomputer. The function of an ICE is to emulate the function of the microcomputer subject to program debugging. An address bus and a data bus of the microcomputer are connected to a memory on the ICE. A host computer controlling the ICE downloads a program executed by the microcomputer to the memory on the ICE so that the microcomputer is operated.
In an LSI having a built-in microcomputer, the program is usually stored in a memory provided in the microcomputer. For this reason, the address bus and the data bus for connection with the memory on the ICE are not provided in the terminals of the LSI.
Therefore, a mode dedicated to connection to the ICE is provided. In this mode, the address bus and the data bus are connected to the memory on the ICE by leading the address bus and the data bus to external terminals of the LSI, so that emulation using the ICE is enabled.
However, since the connection between the ICE and the system LSI requires as many connections as the number of terminals in the microcomputer, connection between the ICE and the system LSI involves difficulties as the speed of the microcomputer and the number of buses are increased. It is to be noted further that various functions for system implementation other microcomputer functions are built into the system LSI with a built-in microcomputer. It is thus difficult to perform emulation of the function of the external terminals of the LSI to which the address bus and the data bus are led for connection with the memory on the ICE.
In this background, recently, a debugging circuit complementing the ICE function is built into the microcomputer and connected to an external debugger via LSI terminals dedicated to debugging.
FIG. 7 is a block diagram showing a related-art microcomputer. Referring to FIG. 7, numeral 1 indicates a microcomputer having a built-in debugging circuit 5; 2 indicates a central processing unit (CPU) of the microcomputer 1; 3 indicates a bus interface; 4 indicates a memory; and 5 indicates a debugging circuit for debugging a program of the microcomputer 1 by inputting and outputting data via an external debugger and a trace bus. The debugging circuit 5 is provided with a DATA terminal for inputting and outputting multi-bit DATA to and from the external debugger, a CLK terminal for inputting and outputting a clock signal CLK, an OE terminal for inputting and outputting a control signal OE for controlling input and output of the DATA and the clock signal CLK, and a SYNC terminal for inputting and outputting a synchronization signal SYNC when the tracing is performed.
Numeral 6 indicates a register control circuit for receiving data from the DATA terminal when the external debugger outputs the data to the DATA terminal and for decoding the data; 7 indicates a download control circuit for receiving a program generated by a host computer via the external debugger and downloading the program to the memory 4; 8 indicates a trace control circuit for notifying the external debugger of the operating status of the CPU 2; 9 indicates a comparator for comparing an address at which the program is executed with preset data in order to recognize the operating condition of the CPU 2; and 10 indicates a register circuit.
A description will now be given of the operation according to the related art.
The debugging circuit 5 built in the microcomputer 1 mainly provides the following functions.
Communication Between the External Debugger and the Debugging Circuit 5
When the external debugger outputs the data to the trace bus under the control of the host computer, the register control circuit 6 of the debugger circuit 5 receives the data via the DATA terminal for decoding so as to determine the destination of the data.
Depending on the result of determination, the register control circuit 6 outputs the data to the download control circuit 7, the trace control circuit 8, the comparator 9 or the register circuit 10.
When the incoming data requests reading of data stored in the register circuit 10, the register control circuit 6 reads the data stored in the register circuit 10.
Downloading
When the external debugger outputs the program generated by the host computer to the trace bus under the control of the host computer, the download control circuit 7 of the debugger circuit 5 receives the program via the DATA terminal.
The download control circuit 7 downloads the program to the memory 4 by using the control bus, the address bus ADCPU, and the data bus DB.
Tracing
The trace control circuit 8 recognizes the operating condition of the CPU 2 by capturing signals on the control bus, the address bus ADCPU and the data bus DB, which connect the CPU 2 and the bus interface 3, and outputs the operating condition of the CPU 2 to the external debugger via the DATA terminal and the trace bus.
Breaking
When the external debugger outputs the address at which the program is executed and the data to the comparator 9 under the control of the host computer, via the CLK terminal, the DATA terminal, the OE terminal and the SYNC terminal, the address and the data being specified by the host computer, the comparator 9 compares the status of the address bus ADCPU with the written address.
When they match, the comparator 9 executes an interrupt processing program downloaded to the memory 4 by outputting an interrupt request to the CPU 2. For example, the comparator 9 enables the CPU 2 and the external debugger to transfer data via the register circuit 10.
The following steps for program debugging are taken using the functions described above.    (1) The host computer generates a program.    (2) The program is downloaded to the memory 4 of the microcomputer 1.    (3) The host computer requests execution of the program and keeps track of the operating conditions of the microcomputer 1 from a trace output from of the debugging circuit 5.    (4) A break interrupt is generated at a program address specified by the host computer. In this interrupt process, the host computer communicates with the debugging circuit 5 via the external debugger so as to learn the status of the microcomputer 1.
FIG. 8 shows the internal construction of the trace control circuit 8 of FIG. 7. Referring to FIG. 8, numeral 11 indicates a branch event generation circuit for generating an event necessary for execution of a branch trace in accordance with a control signal output from the CPU 2 to the control bus to require execution of the branch instruction. Numeral 12 indicates a status generation circuit for generating status information ST indicating the branch trace; 13 indicates an AND circuit for ANDing a synchronization signal SYNC—CPU occurring during the execution and a basic clock P1 of the CPU 2, and for outputting BRAS—CLK. Numeral 14 indicates a branching source address latch for latching a branching source address in synchronization with BRAS—CLK.
Numeral 15 indicates an AND circuit for ANDing an operand fetch signal OPR occurring during the execution and the basic clock P1 of the CPU 2, and for outputting BRAD—CLK; 16 indicates a branching destination address latch for latching, in synchronization with BRAD—CLK, a branching destination address output from the CPU 2 to the address bus ADCPU; 17 indicates a logic circuit for outputting a selector control signal SEL1 in synchronization with a falling edge of a branching destination signal RCLR occurring subsequent to the execution of the branch instruction; and 18 indicates an AND circuit for ANDing the selector control signal SEL1 and the basic clock P1 of the CPU 2, and for outputting a trace memory write signal TRW1.
Numeral 19 indicates a CPU access event generation circuit for generating an event necessary for execution of a memory trace in accordance with a control signal output from the CPU to require execution of an instruction requiring an access to the memory 4; and 20 indicates an OR circuit for ORing the trace memory write signal TRW1 output from the AND circuit 18 of the branch event generation circuit 11 and a trace memory write signal TRW2 output from the access event generation circuit 19.
Numeral 21 indicates a selector for selecting an event output from the branch event generation circuit 11 or an event output from the CPU access event generation circuit 19, and for writing the event in a trace memory 22 for containing the contents of the event. Numeral 23 indicates a trace circuit for reading the contents of the event from the trace memory 22 and outputting the contents to the trace bus via the DATA terminal.
A description will now be given of the operation of the trace control circuit 8. The operation described below is performed when the branch instruction from the CPU 2 is executed. It is assumed here that the address bus ADCPU is a 16-bit bus and the DATA terminal and the trace bus are of a 4-bit construction.
When the CPU 2 outputs the control signal to the control bus to require execution of the branch instruction, the status generation circuit 12 of the branch event generation circuit 11 recognizes the requirement of the branch instruction from the control signal. The status generation circuit 12 generates the status information ST for informing the external debugger that the CPU 2 event is a branch trace.
When the CPU 2 outputs the branching source address to the address bus ADCPU as it outputs the control signal, the branch source address latch 14 latches the branching source address in synchronization with BRAS—CLK output from the AND circuit 13.
When the CPU 2 outputs the branching destination address to the address bus ADCPU subsequent to the output of the branching source address, the branching destination address latch 16 latches the branching destination address in synchronization with BRAD—CLK output from the AND circuit 15.
The branching source address and the branching destination address are absolute addresses in the memory 4 and have a 16-bit resolution.
The selector 21 sequentially captures the contents of the event output from the branch event generation circuit 11, that is, the status information ST, the branching source address and the branching destination address. When the selector control signal SEL1 is brought to a high level, the selector 21 opens its internal gate. When the trace write signal TRW1 is brought to a high level, the selector 21 writes the status information ST, the branching source address and the branching destination address to the trace memory 22.
When the contents of the event output from the branch event generation circuit 11 are written in the trace memory 22, the contents of the event are sequentially read by the trace circuit 23. The trace circuit 23 then outputs the contents of the event to the external debugger via the trace bus and the DATA terminal, in synchronization with the clock signal CLK and the synchronization signal SYNC.
For example, as shown in FIG. 9P, when the synchronization signal SYNC goes high, indicating the head of the event, the trace circuit 23 outputs the status information ST, the branching source address A[15:12], the branching source address A[11:8], the branching source address A[7:4], the branching source address A[3:0], the branching destination address A[15:12], the branching destination address A[11:8], the branching destination address A[7:4] and the branching destination address A[3:0], in the stated order, to the 4-bit DATA terminal.
In this illustration, A[:] indicates bits corresponding to the absolute address. For example, [7:4] indicates absolute address values from the seventh significant bit to the fourth significant bit.
In the illustrated example, a total of nine CLK cycles are required in order to output the event of the branch instruction.
Referring to FIG. 9, P2 indicates a basic block of the CPU 2, OPC indicates an opcode fetch signal occurring during the execution, OPCBUS indicates an opcode, and OPRBUS indicates an operand bus. At the bottom of FIG. 9 is given an example where the branch instruction BRA (with the opcode “80”) causes a jump to the address having a label “TEST—” attached thereto.
Since the trace control circuit according to the related art is constructed as described above, it is necessary to increase the number of the DATA terminals and capacity of the trace memory 22 as the bus width of the address bus ADCPU or the data bus DB is increased and the cycle of instructions being executed is increased for improvement in the speed of the microcomputer 1. However, the number of terminals cannot be increased readily in a highly integrated LSI, making it difficult to adapt for improvement in the speed of the microcomputer 1.